Point Spread Frame-buffer-less HDR ISP IP Core

What Is a Frame-buffer-less HDR ISP?

A Frame-buffer-less HDR ISP is an image signal processor that does not rely on external DDR to store full image frames. Instead, it performs HDR merging and image-quality processing through a Line-to-Line pipeline. Conventional ISPs buffer multiple frames in DDR for HDR fusion and denoising, introducing tens of milliseconds of latency as well as higher BOM cost and system power consumption. Point Spread's Frame-buffer-less HDR ISP performs equivalent processing on-chip through a Deep Pipeline Architecture, processing 1 pixel/clock and supporting high-speed CIS readout.

The IP is delivered as a modular solution. CIS vendors can enable, disable, or tune individual processing modules according to their pixel-array characteristics. It can be integrated directly into a CIS to create a “Smart CMOS Image Sensor (CIS),” or embedded in the imaging pipeline of a SoC or ASIC.

Core IP: Real-time 4K RAW-domain BM3D Denoising IP Core

Before denoising (left, noisy image) and after BM3D IP processing (right, result). Test conditions: single-frame capture; 1/2-inch IMX586; F/1.7; 0.8 μm pixel size.

*Note: Area data is estimated for a 7 nm process; FPGA data comes from a validation instance. Exact test conditions are annotated on the original images to support reproducible customer evaluation.

Applications and Target Customers

The Point Spread Frame-buffer-less HDR ISP is designed for imaging systems that are highly sensitive to latency, power, and cost:

• CIS image sensor vendors (ISP IP licensing and integration): Vendors can integrate the IP directly into their sensors to output high-quality HDR images and create differentiated Smart CMOS Image Sensor (CIS) products.
• Low-latency display for medical endoscopy: Gastrointestinal, respiratory, and neuroendoscopic procedures require extremely low display latency. End-to-end processing in 3 ms supports the surgeon's hand-eye coordination.
• Processing ASICs for AR/AI/MR glasses: The DDR-less HDR ISP architecture significantly reduces ASIC power consumption and size, making it suitable for battery-powered headsets.
• Military and law-enforcement low-latency night vision: NightClear™ Night-vision Enhancement Engine and low latency support electronic rear-view mirrors, night-vision devices, night-vision helmets, and related equipment.
• Intelligent driving and automotive vision: Automotive vision and camera monitor systems (CMS) impose strict requirements on both latency and image quality in adverse weather. The Rain & Haze Enhancement function addresses these conditions directly.
• Other applications: Robots and autonomous mobile equipment, drones and airborne vision, intelligent security monitoring, consumer electronics, and AIoT.

Frequently Asked Questions (FAQ)

Q: How does a Frame-buffer-less (DDR-less) HDR ISP differ from a conventional ISP?

A: Conventional HDR ISPs rely on external DDR to buffer multiple frames for fusion, typically introducing tens of milliseconds of latency while increasing BOM cost and power consumption. Point Spread's Frame-buffer-less HDR ISP performs single-frame HDR and denoising on-chip through a Line-to-Line pipeline, achieving end-to-end latency as low as 3 ms without external DDR.

Q: Can BM3D denoising run in real time?

A: BM3D has traditionally been limited to offline processing because of its high computational complexity. Point Spread has implemented it as a Real-time 4K RAW-domain BM3D Denoising IP Core, using only 0.5 MB of on-chip RAM per 4K frame and approximately 1 mm² at 7 nm (estimated). It has been validated on FPGA using 250K–400K LUTs.

Q: Why do medical endoscopes require a low-latency ISP?

A: Intraoperative display latency directly affects a physician's hand-eye coordination and procedural safety. Point Spread's 3 ms full-pipeline end-to-end latency is well below the human perceptual threshold and supports low-latency display requirements for gastrointestinal, respiratory, and neuroendoscopy.

Q: Is this ISP IP suitable for AR/MR glasses?

A: Yes. ASICs for glasses are highly sensitive to power and area. The DDR-less HDR ISP architecture eliminates external memory and its power consumption, while the Deep Pipeline Architecture can be scaled to the required silicon area. It provides a direct low-power imaging-pipeline solution for head-mounted devices.

Q: How can the IP be evaluated and integrated?

A: The IP is delivered in modular form and supports FPGA prototyping. CIS vendors can configure module parameters for their pixel-array characteristics and embed the IP in a RAW-domain processing pipeline, or license the complete solution for integration into a sensor or SoC.